Size the NMOS and PMOS devices in Fig. 2 so that the output resistance is the same as that of an inverter with an NMOS W/L = 4 and PMOS W/L = 8. (fill in the blank) a) NMOS A W/L = ？ , PMOS A W/L = ？ ; b) NMOS B W/L = ？ , PMOS B W/L = ？ ; c) NMOS C W/L = ？ , PMOS C W/L = ？ ; d) NMOS D W/L = ？ , PMOS D W/L = ？ ; ______
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Mark out all the correct statements below.
A. ) Series NMOS transistors implement “OR” function
B. ) Parallel PMOS transistors implement “NAND” function
C. ) Parallel NMOS transistors implement “NOR” function
D. ) Series PMOS transistors implement “AND” function
Complementary logic gate is a combination of a PUN and a PDN.
A. ) True
B. ) False
The master latch of the negative edge-triggered register is?
A. ) Negative latch
B. ) Positive latch
Tcdreg means the propagation delay in the best case.
A. ) True
B. ) False
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