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Mark out all the correct statements about the DCVSL.
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If X and Y are 2’s compliment: What’s the correct item for blank (d)?
Consider the following abrupt junction diode (m=0.5): Cj0=3x10-3F/m2, AD=1μm2, and Ф0=0.64V. If we apply a reverse bias of -2.5V, what’s the value of the total junction capacitance? (select the nearest value)
What’s the value of the channel capacitance between the gate and source of a MOS transistor working in saturation region?
The delay of critical path for which adder in the following is NOT in linear relation with the number of bits N?
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