题目内容

There are at least ()flip-flops for a modulus-12 counter.

A. 12
B. 3
C. 4
D. 5

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A retriggerable one-shot with an active HIGH output has a pulse width of 20ms and is triggered from a 60 Hz line. The output will be a ().

A. series of 16.7 ms pulses
B. series of 20 ms pulses
C. constant LOW
D. constant HIGH

Three cascaded modulus-10 counters have an overall modulus of ().

A. 30
B. 100
C. 1000
D. 10,000

A 4-bit binary counter has a terminal count of ().

A. 4
B. 10
C. 15
D. 16

Assume the clock for a 4-bit binary counter is 80 kHz. The output frequency of the fourth stage (Q3) is ().

A. 5 kHz
B. 10 kHz
C. 20 kHz
D. 320 kHz